The present invention relates to pre-emphasis circuitry.
As data rates and bandwidth requirements of serial links continue to increase, so does the demand and complexity placed on the transceiver designs to deliver solutions to maximize signal integrity between chips. Normally, the transmission medium more strongly attenuates the higher frequency components of a transmitted signal than the lower frequency components. This variation in the frequency response of the transmission medium yields data-dependent jitter and other inter symbol interference (ISI) effects.
Pre-emphasis is a common technique used, on the transmitter side, to counteract the effects of high frequency losses caused by the transmission medium. Pre-emphasis boosts the higher frequency components of the transmitted signal. This helps equalize the frequency response of the signal received at the receiver. In other words, it reduces the difference between the low-frequency and high-frequency components of the received signal, which counteracts the ISI effects from the transmission medium.
In some pre-emphasis circuitry, particularly those with high parasitic effects (e.g., high parasitic capacitance effects), at higher data rates, the pre-emphasis voltage varies based on variations in the data. These variations degrade the effectiveness of the pre-emphasis circuitry in counteracting the frequency response difference due to the transmission medium.
Embodiments of the pre-emphasis circuitry of the present invention arise in this context.